Lesson 01
The RC network
One resistor, one capacitor, one pole. It is also your scope probe, every CMOS gate input, and the reason edges have rise times. Commit to predictions first, then open the bench and see why.
Predict · 1 of 2 · baseline
When does V(out) reach 90%?
A 1 kHz, 0 → 1 V square wave from a 50 Ω generator drives 1 kΩ into 100 nF. On the scope, drag the cursor to where V(out) crosses 90% of its final value after the rising edge. Estimate it in your head; that's the skill.
Result
Waiting on your call.
Make your mark, then lock it in. The answer, your error and the reason behind it land here, and every view on the bench below lights up.
Engine: in-browser MNA solver, 4,000 timesteps to periodic steady state · max deviation from closed form 0.004% of full scale · cross-checked against LTspice 17.2.4 (macOS) on this lesson's three circuits: transients within 35 µV, Bode within 10⁻⁷ dB and 10⁻⁶°.